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fe atures fast access time : 55ns low power consumption: operating current : 30ma (typ.) standby current : 6 a (typ.) ll-version single 2.7v ~ 5.5v power supply all inputs a nd outputs ttl compatible fully static operation tri-state output data retention voltage : 1.5v (min.) lead free and green pa ck age available package : 44-pin 400 mil tsop-ii 48-ball 6mm x 8mm tfbga general description the as 6c8008 is a 8,388,608-bit low power cmos static random access memory organized as 1,048,576 words by 8 bits. it is fabricated using very high performance, high reliability cmos technology. its standby current is stable within the range of operating temperature. the AS6C8008 is well designed for very low power system applications, and particularly well suited for battery back-up nonvolatile memory application. the a s 6c80 08 operates fr om a sin gl e pow er supply of 2.7v ~ 5.5v and all inputs and outputs are fully ttl compatible product family power dissipation product family operating temperature v cc range speed standb y(i sb1, typ.) operating(icc,typ.) as 6c8008(i) -40 ~ 85 2.7 ~ 5.5v 55ns 6a(ll) 30ma functional block diagram decoder i/o data cir cu it con trol cir cu it 102 4kx8 m emory a rray co lumn i/o a0-a19 vcc vss d q0-dq7 ce# we# oe# ce2 pin description symbol description a0 - a19 address inputs dq0 ? dq7 data inputs/outputs ce#, ce2 chip enable inputs we# write enable input oe# output enable input v cc power supply v ss ground nc no conne ct ion 512kx 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 1 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
pin configuration 8008c6sa a1 a2 a3 a4 nc nc nc d q 0 vcc vss a 1 4 a19 nc d q 6 dq 7 d q 5 vss vcc d q 4 nc d q 1 d q 2 tsop-ii 28 14 13 12 11 10 9 8 7 6 5 4 3 2 1 17 16 15 20 19 18 22 23 24 25 26 27 21 a18 a0 nc nc a5 a6 a7 a 1 0 a 1 1 d q 3 nc a17 a16 a15 a 1 2 a9 34 29 30 31 32 33 44 39 40 41 42 43 35 36 37 38 a 1 3 ce# we# a8 ce2 oe # tfbga nc nc a3 a10a9 a11 a0 a14 a8 a19 w e # d q 0 d q 3 nc a18 vss ce2 a13 nc vcc vcc a15 vss c e # nc d q 7 d q 4 nc a2 oe# a1 a6a5 a4 nc 1 2 3 4 5 6 h g c d e f a b a12 nc a17 a7 a16 nc dq 1 d q 2 nc nc dq6 dq5 nc 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 2 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
absolute maximum ratings parameter symbol rating unit voltage on v cc relative to v ss v t1 -0.5 to 6.5 v voltage on any other pin relative to v ss v t2 -0.5 to v cc +0.5 v operating temperature t a -40 to 85(i grade) storage temperature t stg -65 to 150 power dissipation p d 1 w dc output current i out 50 ma soldering temperature (under 10 sec) t solder 260 *stre sses greater than t hose list ed under ?absolute maximum ratings? may cause permanent damage to t he device. this is a st ress rating only and f unct ional operation of t he device o r any other c onditions above those indicated in the operational sections o f this specifi ca tion is not implied. ex posure to the absolute maximum rating conditions for extended period may affect device reliability. truth table mode ce# ce2 oe# we# i/o operation s upp ly cur rent h x x x high-z i sb1 standby x l x x high-z i sb1 output disable l h h h high-z i cc ,i cc1 read l h l h d out i cc ,i cc1 write l h x l d in i cc ,i cc1 note: h = v ih , l = v il , x = don't care. dc electrical characteristics parameter symbol test condition min. typ. *4 max. unit supply voltage v cc 2.7 3.0 5.5 v input high voltage v ih *1 2.4 - v cc +0.3 v input low voltage v il *2 - 0.2 - 0.6 v input leakage current i li v cc v in v ss - 1 - 1 a output leakage current i lo v cc v out v ss output disabled - 1 - 1 a output high voltage v oh i oh = -1ma 2.4 2.7 - v output low voltage v ol i ol = 2ma - - 0.4 v - 55 - 30 60 ma i cc cycle time = min. ce# = v il an d ce2 = v ih i i/o = 0ma other pins at v il or v ih average operating power supply current i cc1 cycle time = 1 s ce# Q 0.2v and ce2 R R v cc -0.2v i i/o = 0ma other pins at 0.2v or v cc -0.2v - 4 12 ma standby power supply current i sb1 ce# v cc -0.2v or ce2 Q 0.2v other pins at 0.2v or v cc -0.2v - 6 50 a 512kx 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 3 of 11 AS6C8008 1024k x 8 bit super low power cmos sram R R R R
notes: 1. v ih (max) = v cc + 3.0v for pulse width less than 10ns. 2. v il (min) = v ss - 3.0v for pulse width less than 10ns. 3. over/un dershoot specifications are characterized, not 100% tested. 4. typical values are included for reference only and are not guaranteed or tested. t yp ical valued are measured at v cc = v cc (typ.) and t a = 25 ? capacitance (t a = 25 , f = 1.0mhz) parameter symbol min. max unit input capacitance c in - 6 pf input/output capacitance c i/o - 8 pf note : these parameters are guaranteed by device characterization, but not production tested. ac test conditions input pulse levels 0.2v to v cc - 0.2v input rise and fall times 3ns input and output timing reference levels 1.5v output load c l = 30pf + 1ttl, i oh /i ol = -1ma/2ma ac electrical characteristics (1) read cycle as 6c8008 parameter sy m. s y m. unit read cycle time t rc address access time t aa chip enable access time t ace output enable access time t oe chip enable to output in low-z t clz output enable to output in low-z t olz chip disable to output in high-z t chz output disable to output in high-z t ohz output hold from address change t oh (2) write cycle as 6c8008 unit parameter write cycle time t wc address valid to end of write t aw chip enable to end of write t cw address set-up time t as write pulse width t wp write recovery time t wr data to write time overlap t dw data hold from end of write time t dh output active from end of write t ow write to output in high-z t whz *these parameters are guaranteed by device characterization, but not production tested. 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 4 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
timing waveforms read cycle 1 (address controlled) (1,2) dout data valid t oh t aa address t rc previous data valid read cycle 2 (ce# and ce2 and oe# controlled) (1,3,4,5) dout data valid t oh oe# high-z high-z t clz t olz t oe t chz t ohz ce2 t ace ce# t aa address t rc notes : 1. we# is high for read cyc le. 2. device is continuously selected oe# = low, ce# = low ., ce2 = high . 3.address must be valid prior to or coincident with ce# = low , ce2 = high; otherwise t aa is the limiting parameter. 4.t clz , t olz , t chz and t ohz are specified with c l = 5pf. transition is measured 500mv from steady state. 5. at any given temperature and voltage condition, t chz is less than t clz , t ohz is less than t olz. 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 5 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
write cycle 1 (we# controlled) (1,2,3,5,6) dout di n data valid t dw t dh (4) high-z t whz we# t wp t cw t wr t as (4) t ow ce# t aw address t wc ce2 write cycle 2 (ce# and ce2 controlled) (1,2,5,6) dout di n data valid t dw t dh (4) high-z t whz we# t wp t cw ce# t wr t as t aw address t wc ce2 notes : 1. we#, ce# mus t be high or ce2 must be low during all address transitions. 2. a wri te occurs during the overlap of a low ce#, high ce2, low we#. 3. during a we#co ntrolled write cycle with oe# low, t wp must be greater than t whz + t dw to allow the drivers to turn off and data to be pl aced on the bus . 4. during this period, i/o pins are in the output state, and input signals must not be applied. 5. if the ce#low tra nsition and ce2 high transition occurs simultaneously with or after we# low transition, the outputs remain in a high im pedance sta te. 6.t ow and t whz are specified with c l = 5pf. transition is measured 500mv from steady state. 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 6 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
dat a retention characteristics parameter symbol test condition min. typ. max. unit v cc for data retention v dr ce# v cc - 0.2v or ce2 0.2v 1.5 - 5.5 v data retention current i dr v cc = 1.5v ce# v cc - 0.2v or ce2 0.2v other pins at 0.2v or v cc - 0.2v - 4 50 a chip disable to data retention time t cdr see data retention waveforms (below) 0 - - ns recovery time t r t rc * - - ns t rc * = read cycle time dat a retention waveform low vcc data retention waveform (1) ( ce# controlled) vcc ce# v dr 1.5v ce# vcc-0.2v vcc(min.) v ih t r t cdr v ih vcc(mi n.) low vcc data retention waveform (2) (ce2 controlled) vcc ce2 v dr 1.5v ce2 0.2v vcc(min.) v il t r t cdr v il vcc(min.) > _ > _ > _ > _ > _ > _ > _ > _ 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 7 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
package outline dimension 44-pin 400mil tsop-ii package outline dimension dimensions in millmeters di mensions in mils symbols mi n. n om. max. min. nom. max. a - - 1.20 - - 47.2 a1 0.05 0.10 0.15 2.0 3. 9 5. 9 a2 0.95 1.00 1.05 37.4 39.4 41.3 b 0.30 - 0.45 11.8 - 17 .7 c 0.12 - 0.21 4.7 - 8.3 d 18.212 18.415 18.618 717 725 733 e 11.506 11.760 12.014 453 463 473 e1 9.957 10.160 10.363 392 400 408 e - 0.800 - - 31.5 - l 0. 40 0.50 0.60 15.7 19.7 23.6 zd - 0.805 - - 31.7 - y - - 0.076 - - 3 0 o 3 o 6 o 0 o 3 o 6 o 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 8 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
48-ball 6mm 8mm tfbga package outline dimension 512k x 8 bit low power cmos sram january 2007 january 2008 january/2008, v 1.0 alliance memory inc. page 9 of 11 AS6C8008 1024k x 8 bit super low power cmos sram
ordering information 512k x 8 bit low power cmos sram january 2007 1024k x 8 bit low power cmos sram january 2008 AS6C8008 januar/2008, v 1.0 alliance memory inc. page 10 of 11 alliance organization vcc range package operating temp speed ns AS6C8008-55zin 1024k x 8 2.7 - 5.5v 44pin tsop ii industrial ~ -40 c - 85 c 55 AS6C8008-55bin 1024k x 8 2.7 - 5.5v 48ball tfbga industrial ~ -40 c - 85 c 55 part numbering system as6c 8008 -55 x x n device number package option temperature range 380 =8m z - 44pin tsop i = industrial low power s ram prefix 08 = x8 access ti m e b = 48ball tfbga (-40 to + 85 c) n = lead free roh s compliant part
512k x 8 bit low power cmos sram january 2007 1024k x 8 bit low power cmos sram january 2008 AS6C8008 january/2008, v 1.0 alliance memory inc. page 11 of 11 copyright ? alliance memory all rights reserved alliance memory, inc 511 taylor way, san carlos, ca 94070, usa phone: 650-610-6800 fax: 650-620-921 1 www .alliancememory.com ? copyright 2007 alliance memory, inc. all rights reserved. our three-point logo, our name and intelliwatt are trademarks or registered trademarks ofalliance. all other brand and product names may be the trademarks of their respective companies. alliance reserves the right to make changes to thisdocument and its products at any time without notice. alliance assumes no responsibility for any errors that may appear in this document. the datacontained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at anytime, without notice. if the product described herein is under development, significant changes to these specifications are possible. the information inthis product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide,any guarantee or warrantee to any user or customer . alliance does not assume any responsibility or liability arising out of the application or use of anyproduct described herein, and disclaims any express or implied warranties related to the sale and/or use of alliance products including liability orwarranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to inalliance's terms and conditions of sale (which are available from alliance). all sales of alliance products are made exclusively according to alliance'st erms and conditions of sale. the purchase of products from alliance does not convey a license under any patent rights, copyrights; mask works rights,trademarks, or any other intellectual property rights of alliance or third parties. alliance does not authorize its products for use as critical components inlife-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion ofalliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify alliance against allclaims arising from such use. ?

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